Despite EUV ban, Huawei could send 3nm design to SMIC as soon as next year
Should Huawei and SMIC continue to rely on DUV machines, the lithography will require the use of multiple impressions on silicon wafers (double, triple, or even quadruple patterning) which pushes up the cost of making a chip especially as yields decline. The use of multiple impressions results in the transfer of circuitry patterns to silicon wafers that are less precise and sharp as such designs would be using the lithography machines that are blocked from getting shipped to China. This lowers the foundry’s yield and raises the cost of the chips made using this method.
The 5nm Kirin 9000 was made by TSMC in 2020 just before U.S. sanctions hit
The 3nm chips made for Huawei will use Gate-All-Around (GAA) transistors which only Samsung Foundry uses at 3nm. GAA transistors surround the channel with the gate on all four sides reducing current leaks and improving the drive current. The result is a more powerful chip with better performance and energy efficiency. Huawei is also supposed to tinker with the usual silicon design and opt for the use of “two-dimensional” materials which is also supposed to improve chip performance and lower energy consumption.
Aside from these changes, Huawei is believed to be developing a 3nm node that uses carbon nanotubes instead of silicon transistors. The report calls for Huawei to have completed the design phase for its 3nm node next year, which is also known as the “Tape-out” stage. At that point, Huawei sends the completed and verified design to SMIC allowing the foundry to prepare for the manufacturing of chips using the 3nm node.
